Nanostructured material may allow for the creation of novel integrated circuit designs. For example, US Patent Publication 2005/0181587 to Duan et al. discloses the use of nanowires as channel materials in thin film transistors (TFT's).
FIG. 2 shows a prior art TFT 200 from this application that includes thin film of nanowires 100. TFT 200 has a source electrode 202, a gate electrode 204, a drain electrode 206, formed on a substrate 208. Thin film of nanowires 100 is coupled between source electrode 202 and drain electrode 206 over a portion of gate electrode 204. Thin film of nanowires 100 substantially operates as a channel region for the transistor of semiconductor device 200.
In this prior art reference, the nanowires of thin film of nanowires 100 are disclosed to be single crystal semiconductor nanowires that span all the way between source electrode 202 and drain electrode 206 so that electric carriers can transport through the single crystals nanowires, resulting in high mobility which is virtually impossible to obtain with current amorphous and polysilicon technologies.
Duan et al. disclose that the nanowires of thin film of nanowires 100 can be aligned or oriented. For example, the nanowires of thin film of nanowires 100 shown in FIG. 2 can be aligned parallel to the length of the channel between source electrode 202 and drain electrode 206, or can be aligned in alternative ways.
Duan et al. also disclose that thin film of nanowires 100 can be formed with a sufficient number of nanowires to provide desired characteristics for semiconductor device 200. For example, thin film of nanowires 100 can be formed of a sufficient number of nanowires to achieve a desired current density or current level desired for the particular semiconductor device. For instance, in the TFT example of FIG. 2, thin film of nanowires 100 can be formed to have a current level in the channel of greater than about 10 nanoamps.
Additionally, Duan et al. disclose that thin film of nanowires 100 can be formed to have asymmetric mobility. For example, this can be accomplished by asymmetrically aligning the nanowires of thin film of nanowires 100, and/or by doping the nanowires in a particular manner. Such asymmetric mobility can be caused to be much greater in a first direction than in a second direction. For example, asymmetric mobilities can be created in the order of 10, 100, 1000, and 10000 times greater in the first direction than in the second direction, or to have any other asymmetric mobility ratio between, greater, or less than these values.
Thus, TFT's as disclosed by Duan et al. may provide many advantages over traditional semiconductor transistors.
As another example, US Patent Publication 2004/0135951 to Stumbo et al. discloses the use of nanowire enabled transistors for a display driving application.
FIG. 5 is a diagram of a pair of nanowire row transistors within a prior art liquid crystal display (LCD) disclosed by Stumbo et al. This diagram includes nanowire row transistor 510, nanowire row transistor 520, pixel 530, nanowire pixel transistor 540, column trace 550, row trace 560, high trace 570, gate trace 572, low trace 574, and gate trace 576. Nanowire row transistor 510 includes set of nanowires 515. Likewise nanowire row transistor 520 includes set of nanowires 525. Nanowire row transistors 510 and 520 are used to turn nanowire pixel transistor 540 on and off.
Nanowire row transistor 510 has one side of the set of nanowires 515 coupled to row trace 560 and the other side coupled to high trace 570. High trace 570 is connected to a source of operating voltage (e.g. an on voltage). A point on each nanowire between these connections on the set of nanowires 515 that collectively serve as the transistor gate is connected to gate trace 572.
Nanowire row transistor 520 has one side of the set of nanowires 525 coupled to row trace 560 and the other side coupled to low trace 574. Low trace 574 is connected to a source of reference voltage (e.g. ground). A point on each nanowire between these connections on the set of nanowires 525 that collectively serve as the transistor gate is connected to gate trace 576.
When nanowire pixel transistor 560 is to be turned on, a gate voltage is applied over gate trace 572 to turn nanowire row transistor 510 on. At the same time a ground potential is applied over gate trace 576 to turn nanowire row transistor 520 off. As a result, a gate voltage is connected to nanowire pixel transistor gate 545 to turn nanowire pixel transistor 540 on. When nanowire pixel transistor 510 is to be turned off, the opposite occurs. The gate voltage is removed from gate trace 572 to turn nanowire row transistor 510 off. And, at the same time a gate voltage is applied to gate trace 576 to turn nanowire row transistor 520 on. As a result, the gate voltage of nanowire pixel transistor gate 545 is driven to ground potential to turn nanowire pixel transistor 540 off.